Directed Test Generation for Validation of Cache Coherence Protocols

Directed Test Generation for Validation of Cache Coherence Protocols

Computing systems utilize multi-core processors with complex cache coherence protocols to meet the increasing need for performance and energy improvement. It is a major challenge to verify the correctness of a cache coherence protocol since the number of reachable states grows exponentially with the number of cores. In this paper, we propose an efficient test generation technique, which can be ...

Proofs of Correctness of Cache-Coherence Protocols

We describe two proofs of correctness for Cachet, an adaptive cache-coherence protocol. Each proof demonstrates soundness (conformance to an abstract cache memory model CRF) and liveness. One proof is manual, based on a term-rewriting system de nition; the other is machine-assisted, based on a TLA formulation and using PVS. A twostage presentation of the protocol simpli es the treatment of soun...

TLA Verification of Cache-Coherence Protocols

Automatic Verification of Parameterized Cache Coherence Protocols

Dynamic Verification of Cache Coherence Protocols

A method for improving the fault-tolerance of cache coherent multiprocessors is proposed. By dynamically verifying coherence operations in hardware, errors caused by manufacturing faults, soft errors, and design mistakes can be detected. Analogous to the DIVA concept for singleprocessor systems, a simple version of the protocol functions as a checker for the aggressive implementation. An exampl...